( ( nil
  version "2.1"
  mapType "incremental"
  blockName "8bitAdderCompare_TB"
  repList "spectre cmos_sch cmos.sch schematic veriloga"
  stopList "spectre"
  globalList "gnd!"
  hierDelim "."
  netlistDir "/net/plato.ee.Virginia.EDU/users2/arw5vy/simulation/8bitAdderCompare_TB/spectre/schematic/netlist"
 )
( instViewTable
 )
( net
 )
( inst
 )
( model
( "Project/4FOInverter/schematic" "Project_4FOInverter_schematic" )
( "Project/CmosNor/schematic" "CmosNor" )
( "Project/FullAdder/schematic" "FullAdder" )
( "Project/8bitAdderCompare/schematic" "Project_8bitAdderCompare_schematic" )
( "Project/CmosNand/schematic" "CmosNand" )
( "Project/8bitAdderCompare_TB/schematic" "Project_8bitAdderCompare_TB_schematic" )
( "gnd!" "0" )
( "Project/CmosXor/schematic" "CmosXor" )
( "Project/CmosInverter/schematic" "CmosInverter" )
( "Multiplier/Inverter/schematic" "Inverter" )
 )
( term
 )
( param
 )
( "Project_8bitAdderCompare_schematic" "ihnl/cds5/map" )
( "CmosXor" "ihnl/cds3/map" )
( "CmosNor" "ihnl/cds0/map" )
( "CmosNand" "ihnl/cds1/map" )
( "FullAdder" "ihnl/cds4/map" )
( "CmosInverter" "ihnl/cds2/map" )
( "Project_8bitAdderCompare_TB_schematic" "ihnl/cds8/map" )
( "Inverter" "ihnl/cds6/map" )
( "Project_4FOInverter_schematic" "ihnl/cds7/map" )
 )
